This invention relates to the computer display of schematic diagrams, specifically in the context of integrated circuit (“IC”) design.
Electronic design automation (“EDA”) systems assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. These systems generally include a schematic diagram editor, which is usually an interactive tool that produces a graphical representation of the circuit elements and the interconnections among the circuit elements on a graphical display. The schematic diagram editor enables the user to select from a number of circuit elements on the display screen, which is connected to the computer.
The process of designing an IC device is done in several steps on a typical EDA system. One of the steps involves analyzing the schematic diagram of the design to determine if the circuit will perform correctly when it is constructed. If not, the user may then edit the schematic diagram using the schematic diagram editor. This process is performed iteratively until the user is satisfied that the design of the circuit is correct.
In modern digital systems, IC designs incorporating thousands of circuit elements or more are not uncommon. These designs, due to their complexity, result in large and cluttered schematic diagrams that are hard to analyze and debug. Traversing through unwieldy schematic diagrams in search of a particular circuit element or tracing through interconnections can consume a substantial amount of time. FIG. 1 shows an exemplary schematic diagram of a typical IC design. The exemplary schematic diagram is overcrowded with graphical representations of the interconnections among circuit elements, rendering it difficult for a user to analyze the design efficiently. It is, therefore, desirable to have less cluttered schematic diagrams that the user can detect errors and edit iteratively with ease.
Existing methods for displaying schematics of an IC device allow the user to specify one specific interconnection at a time to be hidden. Such a method is used in the Block Editor tool in the Quartus® U software from Altera Corporation in San Jose, Calif. However, this does not offer a practical solution for designs with a large number of interconnections that need to be hidden. In some IC floorplan viewing tools, such as the Floorplan Editor tool in the Quartos® II software, one can hide either all fan-in or all fan-out connections. However, such tools do not apply to displaying schematic diagrams (which show individual circuit element types). Furthermore, when such tools hide connections, they do not allow for representing the hidden connections in an alternative manner that shows the connection with minimal visual clutter.
Therefore, an efficient way of configuring the display of interconnections shown in an IC schematic diagram to control visual clutter is needed.